Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Output Type
Single Ended
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
6.4 ns @ 15 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
X2SON
Pin Count
4
Logic Family
LVC
Dimensions
0.85 x 0.85 x 0.35mm
Maximum Operating Supply Voltage
5.5 V
Height
0.35mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
0.85mm
Width
0.85mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
15pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
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P.O.A.
20
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Output Type
Single Ended
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
6.4 ns @ 15 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
X2SON
Pin Count
4
Logic Family
LVC
Dimensions
0.85 x 0.85 x 0.35mm
Maximum Operating Supply Voltage
5.5 V
Height
0.35mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
0.85mm
Width
0.85mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
15pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22