Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Flip Flop IC
Logic Family
LVC
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface Mount
Package Type
SOIC
Minimum Supply Voltage
1.65V
Pin Count
20
Maximum Supply Voltage
3.6V
Flip-Flop Type
D Flip-Flop
Minimum Operating Temperature
-40°C
Trigger Type
Positive Edge
Maximum Operating Temperature
85°C
Number of Elements per Chip
8
Length
12.8mm
Height
2.35mm
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
€ 8.19
€ 0.819 Each (In a Pack of 10) (Exc. VAT)
Standard
10
€ 8.19
€ 0.819 Each (In a Pack of 10) (Exc. VAT)
Stock information temporarily unavailable.
Standard
10
| Quantity | Unit price | Per Pack |
|---|---|---|
| 10 - 40 | € 0.819 | € 8.19 |
| 50 - 90 | € 0.779 | € 7.78 |
| 100 - 240 | € 0.699 | € 6.99 |
| 250 - 490 | € 0.63 | € 6.30 |
| 500+ | € 0.598 | € 5.98 |
Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Flip Flop IC
Logic Family
LVC
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface Mount
Package Type
SOIC
Minimum Supply Voltage
1.65V
Pin Count
20
Maximum Supply Voltage
3.6V
Flip-Flop Type
D Flip-Flop
Minimum Operating Temperature
-40°C
Trigger Type
Positive Edge
Maximum Operating Temperature
85°C
Number of Elements per Chip
8
Length
12.8mm
Height
2.35mm
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22


