Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Logic Gate
Logic Function
OR
Mount Type
Surface
Number of Elements
1
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Input Type
CMOS
Maximum Propagation Delay Time @ CL
4.5ns
Minimum Operating Temperature
-40°C
Maximum High Level Output Current
-32mA
Maximum Operating Temperature
85°C
Minimum Supply Voltage
1.65V
Width
1.6 mm
Series
SN74
Maximum Supply Voltage
5.5V
Height
1.15mm
Length
2.9mm
Standards/Approvals
No
Maximum Low Level Output Current
32mA
Automotive Standard
No
Output Type
CMOS
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
€ 2.20
€ 0.088 Each (In a Pack of 25) (Exc. VAT)
25
€ 2.20
€ 0.088 Each (In a Pack of 25) (Exc. VAT)
Stock information temporarily unavailable.
25
| Quantity | Unit price | Per Pack |
|---|---|---|
| 25 - 100 | € 0.088 | € 2.20 |
| 125 - 225 | € 0.084 | € 2.11 |
| 250 - 600 | € 0.075 | € 1.88 |
| 625 - 1225 | € 0.068 | € 1.71 |
| 1250+ | € 0.064 | € 1.60 |
Technical Document
Specifications
Brand
Texas InstrumentsProduct Type
Logic Gate
Logic Function
OR
Mount Type
Surface
Number of Elements
1
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Input Type
CMOS
Maximum Propagation Delay Time @ CL
4.5ns
Minimum Operating Temperature
-40°C
Maximum High Level Output Current
-32mA
Maximum Operating Temperature
85°C
Minimum Supply Voltage
1.65V
Width
1.6 mm
Series
SN74
Maximum Supply Voltage
5.5V
Height
1.15mm
Length
2.9mm
Standards/Approvals
No
Maximum Low Level Output Current
32mA
Automotive Standard
No
Output Type
CMOS
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22


