Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
€ 4.01
€ 0.802 Each (In a Pack of 5) (Exc. VAT)
Standard
5
€ 4.01
€ 0.802 Each (In a Pack of 5) (Exc. VAT)
Stock information temporarily unavailable.
Standard
5
Stock information temporarily unavailable.
| Quantity | Unit price | Per Pack |
|---|---|---|
| 5 - 20 | € 0.802 | € 4.01 |
| 25 - 45 | € 0.76 | € 3.80 |
| 50 - 120 | € 0.687 | € 3.44 |
| 125 - 245 | € 0.617 | € 3.08 |
| 250+ | € 0.587 | € 2.93 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22


