Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
2.9 x 1.6 x 1.15mm
Height
1.15mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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€ 0.745
Each (On a Reel of 250) (Exc. Vat)
250
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Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
2.9 x 1.6 x 1.15mm
Height
1.15mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22