Technical Document
Specifications
Brand
NexperiaLogic Function
OR
Mounting Type
Surface Mount
Number Of Elements
2
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
TSSOP
Pin Count
8
Logic Family
LVC
Input Type
TTL
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
6 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Minimum Operating Temperature
-40 °C
Output Type
Single Ended
Length
3.1mm
Height
0.95mm
Width
3.1mm
Dimensions
3.1 x 3.1 x 0.95mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Product details
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
€ 32.13
€ 0.214 Each (Supplied on a Reel) (Exc. VAT)
Production pack (Reel)
150
€ 32.13
€ 0.214 Each (Supplied on a Reel) (Exc. VAT)
Stock information temporarily unavailable.
Production pack (Reel)
150
Stock information temporarily unavailable.
Quantity | Unit price | Per Reel |
---|---|---|
150 - 270 | € 0.214 | € 6.43 |
300 - 720 | € 0.202 | € 6.05 |
750 - 1470 | € 0.186 | € 5.57 |
1500+ | € 0.171 | € 5.12 |
Technical Document
Specifications
Brand
NexperiaLogic Function
OR
Mounting Type
Surface Mount
Number Of Elements
2
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
TSSOP
Pin Count
8
Logic Family
LVC
Input Type
TTL
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
6 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Minimum Operating Temperature
-40 °C
Output Type
Single Ended
Length
3.1mm
Height
0.95mm
Width
3.1mm
Dimensions
3.1 x 3.1 x 0.95mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Product details
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS